As semiconductor devices becomes more highly integrated, trench-type device isolation layers may be used for isolating devices. A trench-type device isolation layer may be formed by forming a trench defining an active region in a region of a semiconductor substrate, and filling the trench with an insulating layer. In comparison with a conventional local oxidation of silicon (LOCOS) isolation layer (in which a “bird's beak” phenomenon may occur), it may be possible to form the trench device isolation layer with a narrower linewidth, so that it may be used in highly integrated semiconductor devices.
A flash memory device may also employ the trench device isolation layer to provide higher integration. The flash memory device may have nonvolatile characteristics such that stored data may be retained even if power thereto is interrupted, as charges may be stored in a floating gate that may be electrically isolated. A conventional method of forming a flash memory device including a trench device isolation layer will be illustrated with reference to FIGS. 1 to 4.
FIGS. 1 to 4 are cross-sectional views illustrating conventional methods of forming flash memory devices having a trench device isolation layer.
Referring to FIG. 1, a buffer oxide layer 2 and a hard mask layer 3 are formed on a semiconductor substrate 1 in sequence. Thereafter, the hard mask layer 3, the buffer oxide layer 2 and the semiconductor substrate 1 are successively patterned to form a trench 4 which defines an active region. The buffer oxide layer 2 may be formed through an oxidation process, and the hard mask layer 3 may be a silicon nitride layer. An oxide layer is deposited over an entire surface of the semiconductor substrate 1 to fill the trench 4. Afterwards, the oxide layer is planarized until the patterned hard mask layer 3 is exposed, to thereby form a device isolation layer 5 which fills the trench 4. For example, the device isolation layer 5 may be a silicon oxide layer formed by a chemical vapor deposition (CVD) process using high-density plasma (HDP).
Referring to FIGS. 2 and 3, the exposed hard mask layer 3 is removed by a wet etching process to expose the patterned buffer oxide layer 2. Thereafter, the exposed buffer oxide layer 2 is also removed by a wet etching process so as to expose the surface of the active region. The buffer oxide layer 2 may be removed by wet etching to reduce the likelihood of damage to the surface of the active region.
While performing the wet etching process (which may be an isotropic etching process) to remove the buffer oxide layer 2, the device isolation layer 5 formed of the silicon oxide layer may also be etched. For example, the buffer oxide layer 2 may be formed by thermal oxidation, and the device isolation layer 5 may be formed of silicon oxide by a CVD process. Accordingly, the device isolation layer 5 may be etched faster than the buffer oxide layer 2 during the wet etching process. Typically, because the silicon oxide layer formed by the oxidation process may have a denser structure than the silicon oxide layer formed by the CVD process, the buffer oxide layer 2 may have a slower etch rate in comparison with the device isolation layer 5 formed by the CVD process.
Because wet etching may be isotropic, and the etch rate of the device isolation layer 5 may be faster than that of the buffer oxide layer 2, a “dent” 6 may be formed at an edge of the device isolation layer 5, as illustrated in FIG. 3. The dent 6 may be formed on the edge of the device isolation layer 5 adjacent to the active region.
Referring to FIG. 4, a tunnel oxide layer 7, a floating gate 8, an oxide-nitride-oxide (ONO) layer 9, and a control gate electrode 10 are formed on the active region in sequence. At this time, the dent 6 may be filled by a bottom portion of the floating gate 8. The portion 11 of the floating gate 8, that may fill the dent 6, may be relatively sharp. Due to the sharp portion 11 of the floating gate 8, operation of the flash memory cell may fail. For example, an electric field may be concentrated at the sharp portion 11 of the floating gate 8. Therefore, when erasing data of the flash memory cell by Fowler-Nordheim (F-N) tunneling, the data may be over-erased due to the sharp portion 11 of the floating gate 8. In addition, as read/write operations are repeated, the sharp portion 11 and/or the tunnel oxide layer 7 adjacent to the sharp portion 11 may be deteriorated, such that the reliability of the flash memory cell may be reduced. This phenomenon may also occur at an edge of the active region. That is, the floating gate 8 may be formed in such a shape that it surrounds the edge of the active region adjacent to the device isolation layer 5. The edge of the active region may be formed in an angular shape due to etching of the trench 4. Accordingly, the electric field may also be concentrated at the angular edge of the active region. Therefore, data may be over-erased due to the angular edge of the active region, and the characteristics of the tunnel oxide layer 7 around the angular edge may be deteriorated.